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RM0008
6.3.7
Note:
Low-, medium- and high-density reset and clock control (RCC)
APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
ADC3
EN
rw
14
USAR
T1EN
rw
13
TIM8
EN
rw
12
SPI1
EN
rw
11
TIM1
EN
rw
10
ADC2
EN
rw
9
ADC1
EN
rw
8
IOPG
EN
rw
7
IOPF
EN
rw
6
IOPE
EN
rw
5
IOPD
EN
rw
4
IOPC
EN
rw
3
IOPB
EN
rw
2
IOPA
EN
rw
1
Res.
0
AFIO
EN
rw
Bits 31:16
Reserved, always read as 0.
Bit 15 ADC3EN: ADC 3 interface clock enable
Set and cleared by software.
0: ADC 3 interface clock disabled
1: ADC 3 interface clock enabled
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 TIM8EN: TIM8 Timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI 1 clock enable
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Bit 11 TIM1EN: TIM1 Timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bit 10 ADC2EN: ADC 2 interface clock enable
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Doc ID 13902 Rev 9
95/995
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